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1 ? fn8196.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005, 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. x9421 low noise/low power/spi bus single digitally controlled (xdcp?) potentiometer description the x9421 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and a four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. power-up recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? single voltage potentiometer ? 64 resistor taps ? spi serial interface for write, read, and transfer operations of the potentiometer ? wiper resistance, 150 typical at 5v ? 4 non-volatile data registers ? non-volatile storage of multiple wiper positions ? power-on recall. loads saved wiper position on power-up. ? standby current < 5a max ?v cc : 2.7v to 5.5v operation ?2.5k , 10k end to end resistance ? 100 yr. data retention ? endurance: 100, 000 data changes per bit per register ? 14 ld tssop, 16 ld soic ? low power cmos ? pb-free available (rohs compliant) block diagram 64-taps 10k inc / dec r h /v h r l /v l r w /v w pot v cc v ss spi bus address data status write read wiper transfer power-on recall wiper counter register (wcr) data registers 4 bytes control interface bus interface & control data sheet january 14, 2009 n o t r e c o m m e n d e d f o r n e w d e s i g n s p o s s i b l e s u b s t i t u t e p r o d u c t i s l 2 2 4 1 6 , i s l 2 2 4 1 9
2 fn8196.4 january 14, 2009 ordering information part number part marking v cc limits (v) potentiometer organization (k ) temp range (c) package X9421YS16* x9421ys 5 10% 2.5 0 to +70 16 ld soic (300 mil) X9421YS16z* (note) x9421ys z 0 to +70 16 ld soic (300 mil) (pb-free) X9421YS16i* x9421ys i -40 to +85 16 ld soic (300 mil) X9421YS16iz* (note) x9421ys zi -40 to +85 16 ld soic (300 mil) (pb-free) x9421yv14* x9421 yv 0 to +70 14 ld tssop (4.4mm) x9421yv14z* (note) x9421 yvz 0 to +70 14 ld tssop (4.4mm) (pb-free) x9421yv14i* x9421 yv i -40 to +85 14 ld tssop (4.4mm) x9421yv14iz* (note) x9421 yvzi -40 to +85 14 ld tssop (4.4mm) (pb-free) x9421ws16* x9421ws 10 0 to +70 16 ld soic (300 mil) x9421ws16z* (note) x9421ws z 0 to +70 16 ld soic (300 mil) (pb-free) x9421ws16i* x9421ws i -40 to +85 16 ld soic (300 mil) x9421ws16iz* (note) x9421ws zi -40 to +85 16 ld soic (300 mil) (pb-free) x9421wv14* x9421 wv 0 to +70 14 ld tssop (4.4mm) x9421wv14z* (note) x9421 wv z 0 to +70 14 ld tssop (4.4mm) (pb-free) x9421wv14i* x9421 wv i -40 to +85 14 ld tssop (4.4mm) x9421wv14iz* (note) x9421 wvzi -40 to +85 14 ld tssop (4.4mm) (pb-free) X9421YS16-2.7* x9421ys f 2.7 to 5.5 2.5 0 to +70 16 ld soic (300 mil) X9421YS16z-2.7* (note) x9421ys zf 0 to +70 16 ld soic (300 mil) (pb-free) X9421YS16i-2.7* x9421 ys g -40 to +85 16 ld soic (300 mil) X9421YS16iz-2.7* (note) x9421 ys zg -40 to +85 16 ld soic (300 mil) (pb-free) x9421yv14-2.7* x9421 yvf 0 to +70 14 ld tssop (4.4mm) x9421yv14z-2.7* (pb-free) x9421 yvzf 0 to +70 14 ld tssop (4.4mm) (pb-free) x9421yv14i-2.7* x9421 yvg -40 to +85 14 ld tssop (4.4mm) x9421yv14iz-2.7* (pb-free) x9421 yvzg -40 to +85 14 ld tssop (4.4mm) (pb-free) x9421ws16-2.7* x9421ws f 10 0 to +70 16 ld soic (300 mil) x9421ws16z-2.7* (note) x9421ws zf 0 to +70 16 ld soic (300 mil) (pb-free) x9421ws16i-2.7* x9421ws g -40 to +85 16 ld soic (300 mil) x9421ws16iz-2.7* (note) x9421ws zg -40 to +85 16 ld soic (300 mil) (pb-free) x9421wv14-2.7* x9421 wvf 0 to +70 14 ld tssop (4.4mm) x9421wv14z-2.7* (pb-free) x9421 wvzf 0 to +70 14 ld tssop (4.4mm) (pb-free) x9421wv14i-2.7* x9421 wvg -40 to +85 14 ld tssop (4.4mm) x9421wv14iz-2.7* (pb-free) x9421 wvzg -40 to +85 14 ld tssop (4.4mm) (pb-free) *add "t1" suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free mate rial sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020 x9421
3 fn8196.4 january 14, 2009 detailed functional diagrams circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltage of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems wiper counter register (wcr) r h /v h r l /v l data r w /v w interface and control circuitry v cc v ss cs sck a0 so si hold wp control 64-taps 10k power-on recall dr0 dr1 dr2 dr3 x9421
4 fn8196.4 january 14, 2009 x9421 (14 ld tssop) top view x9421 (16 ld soic) top view pin assignments pin descriptions host interface pins serial output (so) so is a push/pull serial data out put pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the potentiometer and pot register are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9421. chip select (cs ) when cs is high, the x9421 is deselected and the so pin is at high impedance, and (unles s an internal write cycle is underway) the device will be in the standby state. cs low enables the x9421, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. r w /v w nc vcc a0 hold cs s0 si nc sck r l /v l r h /v h wp vss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 nc so nc cs sck si vss nc vcc r l /v l r h /v h r w /v w isen ao wp nc tssop pin no. soic pin no. symbol description 1 2 so serial data output 2, 3 3, 1, 7, 5 nc no connect 44cs chip select 5 5 sck serial clock 6 6 si serial data input 7 8 vss system ground 89wp hardware write protect 9 10 a0 device address 10 hold device select. pause the serial bus. 11 12 r w /v w wiper terminal of the potentiometer. 12 13 r h /v h high terminal of the potentiometer. 13 14 r l /v l low terminal of the potentiometer. 14 16 vcc system supply voltage x9421
5 fn8196.4 january 14, 2009 device address (a 0 ) the address input is used to set the least significant bit of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9421. a maximum of two devices may occupy the spi serial bus. potentiometer pins v h /r h , v l /r l the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w the wiper output is equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. writing to the wiper counter register is not restricted. system/digital supply (v cc ) vcc is the supply voltage for the system/digital section. vss is the system ground. principles of operation the x9421 is a highly integrat ed microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the xdcp potentiometer. serial interface the x9421 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be con nected together, since they have three state outputs. this can help to re duce system pin count. array description the x9421 is comprised of one resistor array containing 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of the array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within the individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the block diagram of the potentiometer is shown in figure 1. wiper counter register (wcr) the x9421 contains a wiper counter register. the wcr can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be wr itten directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data regist ers via the xfr data register instruction (parallel load); it can be modified one step at a time by the increment/decremen t instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9421 is powered-down. although the register is autom atically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers the potentiometer has four 6-bi t nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, the data registers can be used as regular memory locati ons for system parameters or user preference data. register descriptions table 1. data registers, (6-bit), nonvolatile there are four 6-bit data registers associated with the potentiometer. ? {d5~d0}: these bits are for general purpose nonvolatile data storage or for storage of up to four different wiper values. table 2. wiper counter regi ster, (6-bit), volatile ? {wp5~wp0}: these bits specif y the wiper position of the potentiometer. 0 0 d5 d4 d3 d2 d1 d0 (msb) (lsb) 0 0 wp5wp4wp3wp2wp1wp0 (msb) (lsb) x9421
6 fn8196.4 january 14, 2009 write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions address/identification (id) byte the first byte sent to the x9421 from the host, following a cs going high to low, is called the address or identification byte. the most significant four bits of the slave address are a device type identifier, for the x9 421 this is fixed as 0101[b] (refer to figure 2). the least significant bit in the id byte selects one of two devices on the bus. the physical device address is defined by the state of the a 0 input pin. the x9421 compares the serial data stream with the a ddress input state; a successful compare of the address bit is required for the x9421 to successfully continue the command sequence. the a 0 input can be actively driven by a cmos input signal or tied to v cc or v ss . the remaining three bits in the id byte must be set to 110. instruction byte the next byte sent to the x9421 contains the instruction and register pointer information. the four most significant bits are the instruction. the next two bi ts point to one of four data registers. the format is shown below in figure 3. the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. the last two bits are defined as 0. serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn v h v l v w 8 6 c o u n t e r d e c o d e if wcr = 00[h] then v w = v l if wcr = 3f[h] then v w = v h wiper (wcr) figure 1. detailed potentiometer block diagram 1 0 0 11 0a0 device type identifier device address 1 figure 2. address/identification byte format i1 i2 i3 i0 r1 r0 0 0 register select instructions figure 3. instruction byte format x9421
7 fn8196.4 january 14, 2009 two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. these instructions are: ? xfr data register to wiper counter register ?this instruction transfers the contents of one specified data register to the wiper counter register. ? xfr wiper counter register to data register ?this instruction transfers the contents of the wiper counter register to the specified associated data register. the basic sequence of the two by te instructions is illustrated in figure 4. these two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between the potentiometer and one of its associated registers. five instructions require a th ree-byte sequence to complete. these instructions transfer da ta between the host and the x9421; either between the host and one of the data registers or directly between the host and the wcr. these instructions are: ? read wiper counter register ?read the current wiper position of the pot, ? write wiper counter register ?change current wiper position of the pot, ? read data register ?read the contents of the selected data register; ? write data register ?write a new value to the selected data register. ? read status ?this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the sequence of these operations is shown in figure 5 and figure 6. the final command is increment/decrement. it is different from the other commands, because it?s length is indeterminate. once the command is issued, the master can clock the wiper up and/or down in one resistor segment step; thereby, providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the v h /r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figure 7 and 8. 0101110a0 i3 i2 i1 i0 r1 r0 0 0 sck si cs figure 4. two-byte instruction sequence 0 101 0a0 i3 i2 i1 i0 r1 r0 0 0 scl si 0 0 d5 d4 d3 d2 d1 d0 cs 11 figure 5. three-byte instruction sequence (write) x9421
8 fn8196.4 january 14, 2009 0 101 0a0 i3 i2 i1 i0 r1 r0 0 0 scl si cs 11 s0 0 0 d5 d4 d3 d2 d1 d0 don?t care figure 6. three-byte instruction sequence (read) 0101 110a0 i3 i2 i1 i0 0 0 0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs figure 7. increment/decrement instruction sequence sck si v w inc/dec cmd issued t wrid voltage out figure 8. increment/decrement timing limits x9421
9 fn8196.4 january 14, 2009 table 3. instruction set instruction format notes: 1. ?a0?: stands for the device addresses sent by the master. 2. wpx refers to wiper position data in the wiper counter register ?i?: stands for the increment operation, si held high during active sck phase (high). 3. ?d?: stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) read the contents of the register pointed to by r1 - r0. write data register (dr) write a new value to the register pointed to by r1 - r0. instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 read wiper counter register 1 0 0 1 0 0 0 0 read the contents of the wiper counter register write wiper counter register 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 0 1 1 1/0 1/0 0 0 read the contents of the data register pointed to by r 1 - r 0 write data register 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to by r 1 - r 0 xfr data register to wiper counter register 1 1 0 1 1/0 1/0 0 0 transfer the contents of the data register pointed to by r 1 - r 0 to the wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by r 1 - r 0 increment/decrement wiper counter register 0 0 1 0 0 0 0 0 enable increment/decrement of the wiper counter register read status (wip bit) 0 1 0 1 0 0 0 1 read the status of the internal write cycle, by checking the wip bit. cs falling edge device type identifier device addresses instruction opcode wiper position (sent by x9421 on so) cs rising edge 0101110 a0 1 0 0 1 000000 wp5wp4wp3wp2wp1wp0 cs falling edge device type identifier device addresses instruction opcode data byte (sent by host on si) cs rising edge 0101110 a0 1 0 1 0000000wp5wp4 wp3wp2wp1 wp0 cs falling edge device type identifier device addresses instruction opcode register addresses data byte (sent by x9421 on so) cs rising edge 0101110a0 1 0 1 1r1 r0 0000wp5wp4wp3wp2wp1wp0 cs falling edge device type identifier device addresses instruction opcode register addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 01011 1 0a 0 1100r 1 r 0 0000wp 5 wp 4 wp 3 wp 2 wp 1 wp 0 x9421
10 fn8196.4 january 14, 2009 transfer data register (dr) to wiper counter register (wcr) transfer the contents of the register pointed to by r1 - r0 to the wcr. transfer wiper counter register (wcr) to data register (dr) increment/decrement wiper counter register (wcr) read status cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge 0101110 a0 1 1 0 1 r1 r0 0 0 cs fallin g edge device type identifier device addresses instruction opcode register addresses cs rising edge high-voltage write cycle 0101110a0 1 1 1 0r1r000 cs falling edge device type identifier device addresses instruction opcode increment/decrement (sent by master on sda) cs rising edge 0101110a000100000i/di/d. . . .i/di/d cs falling edge device type identifier device addresses instruction opcode data byte (sent by x9421 on so) cs rising edge 0101110a0 0 1 0 100010000000w ip x9421
11 fn8196.4 january 14, 2009 analog specifications (over recommended operating conditions unless otherwise stated.) absolute maximum rati ngs thermal information supply voltage (v cc limits) x9421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9421-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v voltage on sck, sda any address input with respect to v ss : . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v v = | (v h - v l ) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma any vh/rh, vl/rl, vw/rw . . . . . . . . . . . . . . . . . . . . . vss to vcc thermal resistance (typical, note 1) ja (c/w) 14 lead tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16 lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 temperature under bias . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details symbol parameter test conditions limits min. (note 5) typ. (note 6) max. (note 5) units rtotal end to end resistance tolerance -20 +20 % power rating +25c, each pot 50 mw r w wiper resistance wiper current iw = (v h - v l )/r total , v cc = 5v 150 250 wiper current iw = (v h - v l )/r total , v cc = 3v 400 1000 v term voltage on any v h /r h , v l /r l , v w /r w v ss = 0v v ss v cc v noise ref: 1khz -120 dbv resolution (note 4) (note 5) 1.6 % absolute linearity (note 1) v w(n)(actual) - v w(n)(expected) -1 +1 mi (note 3) relative linearity (note 2) v w(n + 1) - [v w(n) + mi ] -0.2 +0.2 mi (note 3) temperature coefficient of r total (note 5) 300 ppm/c ratio metric temperature coefficient (note 5) 20 ppm/c c h /c l /c w potentiometer capacitances see ?circuit #3 spice macro model? on page 13 10/10/25 pf i al rh, ri, rw leakage current vin = vss to vcc. device is in stand-by mode. 0.1 10 a x9421
12 fn8196.4 january 14, 2009 endurance and data retention capacitance power-up timing power-up requirements (power-up sequencing can affect correct recall of the wiper registers) the preferred powe r-on sequence is as follows: first v cc and then the potentiometer pins, r h , r l , and r w . voltage should not be applied to the potentiometer pins before v cc is applied. the v cc ramp rate specification should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. also, v cc should not reverse polarity by more than 0.5v. recall of wiper position will not be complete until v cc reaches its final value. dc electrical specifications (over the recommended operating conditi ons unless otherwise specified). symbol parameter test conditions limits min (note 5) typ (note 6) max (note 5) units i cc1 v cc supply current (active) f sck = 2mhz, so = open, other inputs = v ss 400 a i cc2 v cc supply current (nonvolatile write) f sck = 2mhz, so = open, other inputs = v ss 3.5 ma i sb v cc current (standby) sck = si = v ss , addr. = v ss 3a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage v cc x 0.7 v cc + 0.3 v v il input low voltage -0.5 v cc x 0.1 v v ol output low voltage i ol = 3ma 0.4 v parameter min units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test typ units test conditions c out (note 5) output capacitance (so) 8 pf v out = 0v c in (note 5) input capacitance (a0, si, and sck) 6 pf v in = 0v symbol parameter min max units t r v cc (note 5) v cc power-up ramp 0.2 50 v/msec notes: 1. absolute linearity is utilized to determi ne actual wiper voltage versus expected vo ltage as determined by wiper position when used as a potentiometer. 2. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 3. mi = rtot/63 or (v h - v l )/63, single pot 4. typical = individual array resolution. 5. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 6. limits should be considered typi cal and are not production tested. 7. this parameter is not production tested. pa rameter established by characterization. x9421
13 fn8196.4 january 14, 2009 ac test conditions equivalent ac load circuit circuit #3 spice macro model i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 100pf sda output 2.7v 100pf 10pf r h r total c h 25pf c w c l 10pf r w r l x9421
14 fn8196.4 january 14, 2009 ac timing high-voltage writ e cycle timing xdcp timing symbol parameter min (note 5) typ (note 6) max (note 5) units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri (7) si, sck, hold and cs input rise time 2 s t fi (7) si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 150 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns symbol parameter typ (note 6) max (note 5) units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min (note 5) max (note 5) units t wrpo wiper response time after the power supply is stable 10 s t wrl wiper response time after instructi on issued (all load instructions) 10 s t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 10 s x9421
15 fn8196.4 january 14, 2009 symbol table timing diagrams input timing output timing waveform inputs outputs must be steady will be steady may change from low to high will change from lo w to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... x9421
16 fn8196.4 january 14, 2009 hold timing xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo ... cs sck si msb lsb v w t wrl ... so high impedance ... cs sck so si addr t wrid high impedance v w ... inc/dec inc/dec ... x9421
17 fn8196.4 january 14, 2009 write protect and device address pins timing applications information 1. electronic potentiometers provide three powerful application advantages: the variability and reliability of a solid-state potentiometer, 2. the flexibility of computer-based digital controls) 3. the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. basic configurations of electronic potentiometers cs wp a0 a1 t wpasu t wpah (any instruction) v r v w v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current v h v l x9421
18 fn8196.4 january 14, 2009 application circuits noninverting amplifier voltage regulator offset voltage adjustment comparator with hysteritisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /cr 1 +r 2 } v o (max) v ll = {r 1 /cr 1 +r 2 } v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } +5v -5v lm308a cascading techniques buffered reference voltage ? + +5v r 1 +v -5v v w v w v out = v w op-07 v w v w +v +v +v x (a) (b) x9421
19 fn8196.4 january 14, 2009 x9421 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8196.4 january 14, 2009 x9421 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m16.3 (jedec ms-013-aa issue c) 16 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.3977 0.4133 10.10 10.50 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 8 0 8 - rev. 1 6/05

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